1. Field of the Invention
The present invention relates to a semiconductor device including transistors, each transistor having a plurality of electrodes.
2. Description of the Background Art
FIG. 14 is a plan view of a conventional semiconductor chip on which a plurality of field effect transistors (FETs) are formed, and shows an electrode arrangement of FETs formed on the semiconductor chip. FIG. 15 is a sectional view of the semiconductor chip when viewed from the side.
As shown in FIG. 14, gate electrodes 5, drain electrodes 6 and source electrodes 7 of FETs are arranged on a semiconductor substrate 1. The gate electrode 5, drain electrode 6 and source electrode 7 are connected to a gate pad 2, drain pad 3 and source pad 4, respectively. The gate pad 2 and source pad 4 are alternately arranged as shown in FIG. 14. A via hole 9 is formed in the source pad 4.
As shown in FIG. 15, the via hole 9 is formed in the semiconductor substrate 1 and under the source pad 4. The via hole 9 is connected to a heat sink 10 attached on a grounded back plane of the semiconductor substrate 1. Thus, the source electrode 7 is grounded through the source pad 4 and the via hole 9.
These semiconductor chips are die-bonded on a substrate of a package by AuSn solder or the like. The gate pad 2 and drain pad 3 are connected to a lead section of the package through a printed board and so on via wire bonding. This forms a DC signal line and an RF signal line.
In the conventional semiconductor chip described above, since the source electrodes 4 are grounded by using the back plane heat sink 10, the via hole 9 for electrically connecting the source electrode to the heat sink 10 must be formed in the semiconductor substrate 1 as shown in FIG. 15, thus to make a structure and manufacturing process of the semiconductor chip more complex.
Further since the source pads 4 for forming the via holes 9 must be formed on the front plane of the semiconductor chip, the gate pads 2 and source pads 4 have to be alternately arranged. Hence, every gate pad 2 must be wire-bonded and therefore the assembly process become complex and the characteristics caused by variation of wire-bonding lengths is degraded.
As shown in FIG. 14, 10 to 20 source electrodes in an FET operating area 8 are grounded for one set via hole 9, and thus a gain is decreased with an increase in source inductance (Ls) in a high-frequency band higher than 10 GHz.
In addition, as shown in FIG. 16, when a semiconductor chip is die-bonded to the substrate of a package by an AuSn solder in assembly of a device, camber occurs due to a difference of thermal expansions between the semiconductor substrate 1 and the back plane heat sink 10, the thickness of solder on each end of the semiconductor chip increases, and the heat resistance of the device disadvantageously increases.